/* eslint-disable */ function Hardware() { return (
{/* HEADER */}
// hardware · systemverilog · cyclone v The display pipeline. Five SystemVerilog modules turn a small table of shape descriptors into 640×480 pixels at 60 Hz. No frame buffer, no DDR — every pixel is computed at the pixel clock and held in a 640-byte line buffer. The scanline rasterizer is a five-state FSM walking 48 shapes per line.
PIXEL CLOCK · 25 MHz HSYNC · 1600 cycles VSYNC · 525 lines PALETTE · 8 → 24 bit SHAPES · 48 entries
{/* PIPELINE DIAGRAM */}
// dataflow From shape table to VGA pin.
{/* PALETTE TABLE */}
// color_palette.sv Thirteen colors.
Two hundred forty-three blanks.

Every pixel in the line buffer is an 8-bit index. At display time, the palette module turns it into 24-bit RGB with a single combinational case. Indices 13–255 are reserved for future plant types and zombie variants.

// hw/color_palette.sv : line 28
// case (index) 8'd0 → 8'd12 ... default: black

{/* MODULES */}
// hw/ — five files do all the work The modules.
{[ { name: "vga_counters.sv", loc: "59 lines", desc: "640×480@60 timing. 50 MHz in → 25 MHz pixel clock. hcount=0..1599, vcount=0..524, hsync, vsync, blank." }, { name: "linebuffer.sv", loc: "48 lines", desc: "Two 640-byte BRAM banks. One displays the current scanline, the other is being drawn. Roles swap at hsync." }, { name: "color_palette.sv", loc: "55 lines", desc: "Combinational 8→24 bit lookup. Hardcoded 13 entries from the MVP palette; rest default to black." }, { name: "shape_table.sv", loc: "117 lines", desc: "48 entries × {type, visible, x, y, w, h, color}. Shadow / active register file with vsync-edge latch." }, { name: "shape_renderer.sv", loc: "262 lines", desc: "The big one. 5-state FSM rasterizes rect, circle, 7-seg digit, and 32×32 sprite per scanline. Painter's order." }, { name: "pvz_top.sv", loc: "238 lines", desc: "Avalon-MM agent. Wires the shape table, renderer, line buffer, palette, and VGA timing into one peripheral." }, ].map(m => )}
{/* SCANLINE ANATOMY */}
// shape_renderer.sv — anatomy of one scanline One scanline, ~1600 pixel clocks.

The rasterizer is a 5-state FSM. It fills the line with the current cell's background color, then walks all 48 shapes — checking, drawing, advancing. Later shapes overwrite earlier ones (painter's algorithm). The whole thing must finish before the line buffer swap at the next hsync.

{/* AVALON REGISTERS */}
// avalon-mm · 0xff200000 Five 32-bit registers. Memory-mapped on the lightweight HPS-to-FPGA bridge. The kernel module exposes them as /dev/pvz. Three ioctls cover the entire interface: write a background cell, write a shape entry, commit. BASE · 0xff200000
{/* TIMING + TESTBENCHES */}
// quartus build · timing Synthesis & testbenches.

Quartus Prime targets the Cyclone V SE on the DE1-SoC. Five self-checking ModelSim testbenches cover the pipeline end-to-end with a 200 ms watchdog on the integration test.

{`# hw/Makefile targets $ make qsys # qsys-generate → soc_system/ $ make quartus # full synthesis → soc_system.sof $ make rbf # .sof → SD-card .rbf $ make dtb # sopc2dts → device tree blob # ModelSim — five self-checking benches $ vsim -do "run -all; quit" work.tb_vga_counters $ vsim -do "run -all; quit" work.tb_linebuffer $ vsim -do "run -all; quit" work.tb_bg_grid $ vsim -do "run -all; quit" work.tb_shape_renderer $ vsim -do "run -all; quit" work.tb_pvz_top`}
); } /* ───────── pipeline diagram ───────── */ function PipelineDiagram() { return (
); } function PipeBox({ color, name, lines, dark }) { return (
{name.toUpperCase()}
); } function Arrow({ label, sub, color }) { return (
{label}
→
{sub}
); } /* ───────── palette ───────── */ function PaletteGrid() { const palette = [ [ 0, "#000000", "BLACK", "background / unused"], [ 1, "#1B5E20", "DARK GREEN", "grid cell — dark"], [ 2, "#2D8B2D", "LIGHT GREEN", "grid cell — light"], [ 3, "#8B4513", "BROWN", "soil / stem"], [ 4, "#FFD700", "YELLOW", "cursor highlight"], [ 5, "#FF0000", "RED", "zombie body"], [ 6, "#8B0000", "DARK RED", "zombie head"], [ 7, "#008000", "GREEN", "peashooter body"], [ 8, "#006400", "DARK GREEN 2", "peashooter stem"], [ 9, "#00FF00", "BRIGHT GREEN", "pea projectile"], [10, "#FFFFFF", "WHITE", "HUD digits"], [11, "#808080", "GRAY", "HUD background"], [12, "#FFA500", "ORANGE", "sun indicator"], ]; return (
// hw/color_palette.sv 13 / 256 used
{palette.map(([idx, hex, name, use]) => (
{`pal[${String(idx).padStart(2,"0")}]`}
{name}
// {use}
))}
); } /* ───────── module cards ───────── */ function ModuleCard({ name, loc, desc }) { return (
{name} {loc}
{desc}
); } /* ───────── FSM rows ───────── */ function FSMRow({ code, body }) { return (
  • {code} {body}
    • ); } /* ───────── shape types panel ───────── */ function ShapeTypesPanel() { return (
    // SHAPE TYPES — type[1:0]
    0 · RECT
    filled rectangle, w × h, color
    always hit
    1 · CIRCLE
    distance² ≤ (w/2)²
    peas
    2 · 7-SEG DIGIT
    20 × 30 px, val in w[3:0]
    HUD sun
    3 · SPRITE
    32×32 ROM @ 2× → 64×64; pal[0xFF] = transparent
    M2
    ); } function ShapePreview({ kind }) { const box = { width: 48, height: 36, border: "2px solid var(--silicon-600)", background: "#000", position: "relative" }; if (kind === "rect") return
    ; if (kind === "circle") return (
    ); if (kind === "digit") return (
    5
    ); return (
    ); } /* ───────── register table ───────── */ function RegisterTable() { const rows = [ ["0x00", "BG_CELL", "background grid cell color (row, col, color)"], ["0x04", "SHAPE_ADDR", "shape table entry select (0–47)"], ["0x08", "SHAPE_DATA0", "type[1:0] · visible · x[9:0] · y[8:0]"], ["0x0C", "SHAPE_DATA1", "w[8:0] · h[8:0] · color[7:0]"], ["0x10", "SHAPE_COMMIT", "latch shadow → active at next vsync"], ]; return (
    // pvz.h — Avalon register byte offsets 0xff200000
    {rows.map((r,i) => ( ))}
    OFFSET NAME DESCRIPTION
    {r[0]} {r[1]} {r[2]}
    ); } function TBRow({ tb, note }) { return (
    {tb}
    {note}
    ); } window.Hardware = Hardware;